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Ch5_MARTE.pdf | 2018-04-06 16:31 | 2.4M | ||
Ch27_Micro-levelSoCd..> | 2018-04-06 16:52 | 2.1M | ||
Ch18_MPSoC_Prototypi..> | 2018-04-06 16:44 | 2.0M | ||
Ch22_Assertion-based..> | 2018-04-06 16:47 | 1.7M | ||
Ch11_ReconfugurableA..> | 2018-04-06 16:37 | 1.6M | ||
Ch26_Memory-awareOpt..> | 2018-04-06 16:51 | 1.6M | ||
Ch4_ForSyDe.pdf | 2018-04-06 16:30 | 1.4M | ||
Ch13_MemoeryArch.pdf | 2018-04-06 16:38 | 1.4M | ||
Ch28_MAPS.pdf | 2018-04-06 16:52 | 1.3M | ||
Ch7_HybridDSE.pdf | 2018-04-06 16:33 | 1.2M | ||
Ch20_SoftwareTimingS..> | 2018-04-06 16:45 | 1.2M | ||
Ch38_WSN.pdf | 2018-04-06 17:00 | 1.2M | ||
Ch3_SysteMoC.pdf | 2018-04-06 16:29 | 1.2M | ||
Ch31_SCE.pdf | 2018-04-06 16:54 | 1.2M | ||
Ch39_TTA.pdf | 2018-04-06 17:01 | 1.2M | ||
Ch34_SynopsysVirtual..> | 2018-04-06 16:57 | 1.1M | ||
Ch16_NoC-based_Archi..> | 2018-04-06 16:41 | 1.1M | ||
Ch36_DSPCAD.pdf | 2018-04-06 16:59 | 1.1M | ||
Ch32_Metamodeling.pdf | 2018-04-06 16:55 | 1.1M | ||
Ch29_HOPES.pdf | 2018-04-06 16:53 | 1.1M | ||
Ch23_CPA.pdf | 2018-04-06 16:48 | 1.1M | ||
Ch8_CrossLayerDSE.pdf | 2018-04-06 16:34 | 1.1M | ||
Ch33_CadenceTechnolo..> | 2018-04-06 16:56 | 1.0M | ||
Ch25_HW-awareCompila..> | 2018-04-06 16:50 | 1.0M | ||
Ch10_RunTimeDSE.pdf | 2018-04-06 16:36 | 925K | ||
Ch17_ParallelSimulat..> | 2018-04-06 16:42 | 913K | ||
Ch37_CodesignCPS.pdf | 2018-04-06 17:00 | 909K | ||
Ch9_ScenarioDSE.pdf | 2018-04-06 16:35 | 884K | ||
Ch30_DAEDALUS.pdf | 2018-04-06 16:54 | 845K | ||
Ch12_ApplSpecProcess..> | 2018-04-06 16:38 | 796K | ||
Ch2_Quartz.pdf | 2018-04-06 16:28 | 774K | ||
Ch35_GreenDatacenter..> | 2018-04-06 16:59 | 764K | ||
Ch15_NoC_Design.pdf | 2018-04-06 16:40 | 718K | ||
Ch21_TimingModels.pdf | 2018-04-06 16:47 | 705K | ||
Ch19_HostCompiledSim..> | 2018-04-06 16:44 | 701K | ||
Ch24_NetworkedRealTi..> | 2018-04-06 16:49 | 677K | ||
Ch6_OptimizationDSE.pdf | 2018-04-06 16:32 | 614K | ||
Ch14_EmergingMemory.pdf | 2018-04-06 16:39 | 507K | ||
list_of_papers.txt | 2019-01-29 16:13 | 3.2K | ||